CLKSEL=CLKSEL_31P25K, CONV_MODE=BURST, VREF_SEL=INT_1P2V
ADC control register
| ENABLE | ADC enable. Write 1 to Writing 1 before starting conversion and 0 to end conversion. |
| CONV_MODE | ADC conversion mode 0 (BURST): burst conversion 1 (SINGLE): single conversion |
| SCAN_EN | 1 to enable scan mode |
| WCMP_EN | 1 to enable window compare |
| SW_START | Software start ADC conversion write1 to trigger one time ADC conversion, no need clear. |
| CLKSEL | Sigma-Delta ADC clock select 0 (CLKSEL_31P25K): 31P25K 4 (CLKSEL_62P5K): 62P5K 8 (CLKSEL_125K): 125K 12 (CLKSEL_250K): 250K 16 (CLKSEL_500K): 500K 20 (CLKSEL_1M): 1M 24 (CLKSEL_2M): 2M 29 (CLKSEL_32K): 32K |
| SIG_INV_EN | 1 to invert Signma-Delta input signal |
| VREF_SEL | Sigma-Delta ADC Reference source selection. 0 (INT_1P2V): Internal vref 1.2V 1 (EXT_DRV): External VREF 2 (EXT_NO_DRV): Vext without driver 3 (VCC): VCC |
| CH_IDX_EN | 1 to append channel index in data result to be used in scan mode |
| DATA_FORMAT | Data output format. When DATA_FORMAT ==0, When CH_IDX_EN ==0, the ADC_DATA[31:0] is adc data, signed data, 31 bit frac. When CH_IDX_EN ==1, the ADC_DATA[4:0] is channel output, {ADC_DATA[31:5],5’h0} is adc data, signed data, 31 bit frac. When DATA_FORMAT ==1, When CH_IDX_EN ==0, the ADC_DATA[22:0] is adc data, signed data, 22 bit frac. When CH_IDX_EN ==1, the ADC_DATA[31:27] is channel output, ADC_DATA[22:0] is adc data, signed data, 22 bit frac. |
| VREFO_EN | 1 to enable bandgap out-chip capacitor |
| SRST_DIS | 1 to disable adc reset. |
| TRIGGER | Adc start trigger. 0 to 31 PA00 to PA31; 32 to 34 GPIOB0 to GPIOB2; 35, software trigger; 36, rng trigger; 56 to 59, timer 0 to timer 3; 60 to 63 pwm 0 to pwm 3 |